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DATA SHEET
MOS INTEGRATED CIRCUIT
PD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY 4M-WORD BY 16-BIT (WORD MODE) PAGE MODE
Description
The PD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire chip can be erased. Memory organization is 4,194,304 words x 16 bits, so that the memory can be programmed in word units. PD29F064115-X can be read high speed with page mode. The PD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits. Input /output voltage is supplied to 2.7 to 3.3 V. Because the PD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In addition, program code that controls the flash memory can be also stored, and the program code can be programmed or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which can be erased in 4K words units. Once a program or erase command sequence has been executed, an automatic program or automatic erase function internally executes program or erase and verification automatically. The programming time is about 0.5 seconds per sector. The erase time is less than 1 second per sector. Because the PD29F064115-X can be electrically erased or programmed by writing an instruction, data can be reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of applications. This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
Features
* Four bank organization enabling simultaneous execution of program / erase and read * High-speed read with page mode * Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits) * Memory organization : 4,194,304 words x 16 bits * Sector organization : 142 sectors (4K words x 16 sectors, 32K words x 126 sectors) The boot sector is located at the highest address (sector) and the lowest address (sector) * 3-state output * Automatic program * Program suspend / resume * Unlock bypass program * Automatic erase * Chip erase * Sector erase (sectors can be combined freely) * Erase suspend / resume * Program / Erase completion detection * Detection through data polling and toggle bits * Detection through RY (/BY) pin
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M16062EJ2V0DS00 (2nd edition) Date Published September 2002 NS CP (K) Printed in Japan
The mark # shows major revised points.
(c)
2002
PD29F064115-X
* Sector group protection * Any sector group can be protected * Any protected sector group can be temporary unprotected * Any sector group can be unprotected * Sectors can be used for boot application * Hardware reset and standby using /RESET pin * Automatic sleep mode * Boot block sector protect by /WP (ACC) pin * Extra One Time Protect Sector provided
PD29F064115
Access time ns (MAX.) Operating supply voltage V Chip VCC -DB80X, -DB85X -EB80X
Note
Power supply current (MAX.) At active Read 20 15 mA At standby A
I/O VCCQ 3.0 0.3
Program / Erase 35 25 25
80, 85 80
Note
1.95 0.15 1.8 0.15
, -EB85X, -EB90X
, 85, 90
Note Under Development * Program / erase time * Program : 11.0 s / word (TYP.) * Sector erase : Program / erase cycle : 100,000 cycle 0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector) Program / erase cycle : 300,000 cycle 0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector) * Program / erase cycle : 300,000 cycle (MIN.)
Ordering Information
Part number Access time ns (MAX.) Operating supply voltage V Chip VCC I/O VCCQ 3.0 0.3 Operating temperature C -25 to +85 48-pin PLASTIC TSOP (I) (12 x 20) (Normal bent) 63-pin TAPE FBGA (11 x 8) Package
PD29F064115GZ-DB80X-MJH PD29F064115GZ-DB85X-MJH PD29F064115F9-DB80X-CD6 PD29F064115F9-DB85X-CD6 PD29F064115F9-DB80X-CD5 PD29F064115F9-DB85X-CD5 PD29F064115GZ-EB85X-MJH PD29F064115GZ-EB90X-MJH PD29F064115F9-EB85X-CD6 PD29F064115F9-EB90X-CD6 PD29F064115F9-EB85X-CD5 PD29F064115F9-EB90X-CD5
80 85 80 85 80 85 85 90 85 90 85 90
1.95 0.15
85-pin TAPE FBGA (11 x 8)
1.8 0.15
48-pin PLASTIC TSOP (I) (12 x 20) (Normal bent) 63-pin TAPE FBGA (11 x 8)
85-pin TAPE FBGA (11 x 8)
2
Data Sheet M16062EJ2V0DS
PD29F064115-X
Pin Configurations
/xxx indicates active low signal. 48-pin PLASTIC TSOP (I) (12 x 20) (Normal bent) [ PD29F064115GZ-DB80X-MJH ] [ PD29F064115GZ-DB85X-MJH ] [ PD29F064115GZ-EB85X-MJH ] [ PD29F064115GZ-EB90X-MJH ]
Marking Side
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 /WE /RESET A21 /WP (ACC) RY (/BY) A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 /OE GND /CE A0
A0 to A21 /CE /WE /OE /RESET RY (/BY) /WP (ACC) VCC VCCQ GND
: Address inputs : Chip Enable : Write Enable : Output Enable : Hardware reset input : Ready (Busy) output : Write Protect (Accelerated) input : Supply Voltage : Input / Output Supply Voltage : Ground
I/O0 to I/O15 : Data Inputs / Outputs
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M16062EJ2V0DS
3
PD29F064115-X
63-pin TAPE FBGA (11 x 8) [ PD29F064115F9-DB80X-CD6 ] [ PD29F064115F9-DB85X-CD6 ] [ PD29F064115F9-EB85X-CD6 ] [ PD29F064115F9-EB90X-CD6 ]
Top View Bottom View
8 7 6 5 4 3 2 1
ABCDEFGH J K LM
MLKJHGFEDCBA
Top View
A B C D E F G H J K L M
8 7 6 5 4 3 2 1
NC NC
NC NC A13 A9 /WE A12 A8 /RESET A14 A10 A21 A18 A6 A2 A15 A11 A19 A20 A5 A1 A16 I/O7 I/O5 I/O2 I/O0 A0 VCCQ I/O14 I/O12 I/O10 I/O8 /CE I/O15 I/O13 VCC I/O11 I/O9 /OE GND I/O6 I/O4 I/O3 I/O1 GND
NC NC
NC NC
RY(/BY) /WP(ACC) A7 NC NC NC A3 A17 A4
NC NC
NC NC
A0 to A21 /CE /WE /OE /RESET RY (/BY) /WP (ACC) VCC VCCQ GND NC
Note
: Address inputs : Chip Enable : Write Enable : Output Enable : Hardware reset input : Ready (Busy) output : Write Protect (Accelerated) input : Supply Voltage : Input / Output Supply Voltage : Ground : No Connection
I/O0 to I/O15 : Data Inputs / Outputs
Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark.
4
Data Sheet M16062EJ2V0DS
PD29F064115-X
85-pin TAPE FBGA (11 x 8) [ PD29F064115F9-DB80X-CD5 ] [ PD29F064115F9-DB85X-CD5 ] [ PD29F064115F9-EB85X-CD5 ] [ PD29F064115F9-EB90X-CD5 ]
Top View Top View
10 9 8 7 6 5 4 3 2 1
Bottom View Bottom View
ABCDEFGHJKLM ABCDEFGH A 10 9 8 7 6 5 4 3 2 1 NC NC NC NC B NC A NC 8 NC 7 6 NC 5 NC 4 3 NC 2 NC 1 NC C D E
MLKJHGFEDCBA
Top View
F NC D NC NC A14 A14 A10 A10 G NC E A16 A16 NC SA I/O6 I/O6
HGFEDCBA H J K L NC G H F NC GND CIOf VSS I/O15 I/O14 I/O7 I/O15, A-1 I/O7 I/O14 I/O13 I/O12 I/O5 I/O12 I/O5 I/O13 VCCQ I/O4 NC I/O4 CIOs VCCs I/O3 I/O11 VCC VCCf I/O3 I/O11 I/O2 I/O9 I/O10 I/O9 I/O10 I/O2 I/O0 /OE I/O8 /OE I/O0 I/O8 NC /CE /CEf /CE1s NC NC M NC NC
Top View
B C A15 A21 A15 NC A12 A11 A13 A11 A13 A12 A19 A9 A8 A8 A19 A9 /WE NC A20 CE2s A20 /WE /WP(ACC) /RESET RY(/BY) /WP(ACC) /RESET RY(/BY) A18 A17 NC NC A18 A17 /LB /UB A4 A6 A7 A5 A7 A6 A5 A4 A2 A1 A3 A3 A2 A1 NC NC
NC NC
I/O1 I/O1 GND VSS A0 A0 NC
NC NC NC NC NC
A0 to A21 /CE /WE /OE /RESET RY (/BY) /WP (ACC) VCC VCCQ GND NC
Note
: Address inputs : Chip Enable : Write Enable : Output Enable : Hardware reset input : Ready (Busy) output : Write Protect (Accelerated) input : Supply Voltage : Input / Output Supply Voltage : Ground : No Connection
I/O0 to I/O15 : Data Inputs / Outputs
Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark.
INPUT / OUTPUT PIN FUNCTION Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Data Sheet M16062EJ2V0DS
5
PD29F064115-X
Block Diagram
VCC VCCQ GND
Bank C address
Address latch
A0 to A21
Address buffers
Bank A address
Address latch
X-decoder
Cell matrix (Bank A)
X-decoder
Cell matrix (Bank C)
Y-decoder
Y-gating
Y-decoder
Y-gating
Bank / Sector decoder /WP(ACC) Program / Erase voltage generator /RESET /WE /CE /OE SA / WC State control (Command register) SA / WC I/O0 to I/O15
Data latch circuit
Input / Output buffers
RY(/BY)
Address latch
Y-decoder
Y-gating
Y-decoder
Y-gating
Bank B address
X-decode
Cell matrix (Bank B)
Address latch
X-decoder
Cell matrix (Bank D)
Bank D address
6
Data Sheet M16062EJ2V0DS
PD29F064115-X
Sector Organization / Sector Address Table
Bank Sector Organization K words 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Bank C 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Sectors Address SA141 SA140 SA139 SA138 SA137 SA136 SA135 SA134 SA133 SA132 SA131 SA130 SA129 SA128 SA127 SA126 SA125 SA124 SA123 SA122 SA121 SA120 SA119 SA118 SA117 SA116 SA115 SA114 SA113 SA112 SA111 SA110 SA109 SA108 SA107 SA106 Sector Address Table
Bank Address Table
(1/4)
Bank D
3FFFFFH 3FF000H 3FEFFFH 3FE000H 3FDFFFH 3FD000H 3FCFFFH 3FC000H 3FBFFFH 3FB000H 3FAFFFH 3FA000H 3F9FFFH 3F9000H 3F8FFFH 3F8000H 3F7FFFH 3F0000H 3EFFFFH 3E8000H 3E7FFFH 3E0000H 3DFFFFH 3D8000H 3D7FFFH 3D0000H 3CFFFFH 3C8000H 3C7FFFH 3C0000H 3B7FFFH 3B8000H 3B7FFFH 3B0000H 3AFFFFH 3A8000H 3A7FFFH 3A0000H 39FFFFH 398000H 397FFFH 390000H 38FFFFH 388000H 387FFFH 380000H 37FFFFH 378000H 377FFFH 370000H 36FFFFH 368000H 367FFFH 360000H 35FFFFH 358000H 357FFFH 350000H 34FFFFH 348000H 347FFFH 340000H 33FFFFH 338000H 337FFFH 330000H 32FFFFH 328000H 327FFFH 320000H 31FFFFH 318000H
A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
A18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0
A17 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
A16 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
A15 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A14 1 1 1 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A13 1 1 0 0 1 1 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A12 1 0 1 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Data Sheet M16062EJ2V0DS
7
PD29F064115-X
Sector Organization / Sector Address Table
Bank Sector Organization K words 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Sectors Address SA105 SA104 SA103 SA102 SA101 SA100 SA99 SA98 SA97 SA96 SA95 SA94 SA93 SA92 SA91 SA90 SA89 SA88 SA87 SA86 SA85 SA84 SA83 SA82 SA81 SA80 SA79 SA78 SA77 SA76 SA75 SA74 SA73 SA72 SA71 Sector Address Table
Bank Address Table
(2/4)
Bank C
317FFFH 310000H 30FFFFH 308000H 307FFFH 300000H 2FFFFFH 2F8000H 2F7FFFH 2F0000H 2EFFFFH 2E8000H 2E7FFFH 2E0000H 2DFFFFH 2D8000H 2D7FFFH 2D0000H 2CFFFFH 2C8000H 2C7FFFH 2C0000H 2BFFFFH 2B8000H 2B7FFFH 2B0000H 2AFFFFH 2A8000H 2A7FFFH 2A0000H 29FFFFH 298000H 297FFFH 290000H 28FFFFH 288000H 287FFFH 280000H 27FFFFH 278000H 277FFFH 270000H 26FFFFH 268000H 267FFFH 260000H 25FFFFH 258000H 257FFFH 250000H 24FFFFH 248000H 247FFFH 240000H 23FFFFH 238000H 237FFFH 230000H 22FFFFH 228000H 227FFFH 220000H 21FFFFH 218000H 217FFFH 210000H 20FFFFH 208000H 207FFFH 200000H
A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A20 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A19 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A18 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
A17 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
A16 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
A14 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A13 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A12 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
8
Data Sheet M16062EJ2V0DS
PD29F064115-X
Sector Organization / Sector Address Table
Bank Sector Organization K words 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Sectors Address SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 SA37 SA36 SA35 Sector Address Table
Bank Address Table
(3/4)
Bank B
1FFFFFH 1F8000H 1F7FFFH 1F0000H 1EFFFFH 1E8000H 1E7FFFH 1E0000H 1DFFFFH 1D8000H 1D7FFFH 1D0000H 1CFFFFH 1C8000H 1C7FFFH 1C0000H 1BFFFFH 1B8000H 1B7FFFH 1B0000H 1AFFFFH 1A8000H 1A7FFFH 1A0000H 19FFFFH 198000H 197FFFH 190000H 18FFFFH 188000H 187FFFH 180000H 17FFFFH 178000H 177FFFH 170000H 16FFFFH 168000H 167FFFH 160000H 15FFFFH 158000H 157FFFH 150000H 14FFFFH 148000H 147FFFH 140000H 13FFFFH 138000H 137FFFH 130000H 12FFFFH 128000H 127FFFH 120000H 11FFFFH 118000H 117FFFH 110000H 10FFFFH 108000H 107FFFH 100000H 0FFFFFH 0F8000H 0F7FFFH 0F0000H 0EFFFFH 0E8000H 0E7FFFH 0E0000H
A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
A19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
A18 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
A17 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
A14 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A13 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
A12 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Data Sheet M16062EJ2V0DS
9
PD29F064115-X
Sector Organization / Sector Address Table
Bank Sector Organization K words 32 32 32 32 32 32 32 32 32 32 32 32 Bank A 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Address Sectors Address SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Table
Bank Address Table
(4/4)
Bank B
0DFFFFH 0D8000H 0D7FFFH 0D0000H 0CFFFFH 0C8000H 0C7FFFH 0C0000H 0BFFFFH 0B8000H 0B7FFFH 0B0000H 0AFFFFH 0A8000H 0A7FFFH 0A0000H 09FFFFH 098000H 097FFFH 090000H 08FFFFH 088000H 087FFFH 080000H 07FFFFH 078000H 077FFFH 070000H 06FFFFH 068000H 067FFFH 060000H 05FFFFH 058000H 057FFFH 050000H 04FFFFH 048000H 047FFFH 040000H 03FFFFH 038000H 037FFFH 030000H 02FFFFH 028000H 027FFFH 020000H 01FFFFH 018000H 017FFFH 010000H 00FFFFH 008000H 007FFFH 007000H 006FFFH 006000H 005FFFH 005000H 004FFFH 004000H 003FFFH 003000H 002FFFH 002000H 001FFFH 001000H 000FFFH 000000H
A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A19 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A18 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0
A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
A14 x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 0 0 0 0
A13 x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 0 0 1 1 0 0
A12 x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 0 1 0 1 0 1 0
10
Data Sheet M16062EJ2V0DS
PD29F064115-X
Sector Group Address Table
Sector group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 A21 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 0 1 1 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x x x x x x x x x x x x x x A15 0 0 0 0 0 0 0 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) 128K words (4 Sectors) SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 A14 0 0 0 0 1 1 1 1 x A13 0 0 1 1 0 0 1 1 x A12 0 1 0 1 0 1 0 1 x Size 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 96K words (3 Sectors)
(1/2)
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10
Remark x : VIH or VIL
Data Sheet M16062EJ2V0DS
11
PD29F064115-X
Sector Group Address Table
Sector group SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 x x x x x x x x x x x x x x x 0 0 1 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A15 x x x x x x x x x x x x x x x 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) 4K words (1 Sector) SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 A14 x x x x x x x x x x x x x x x x A13 x x x x x x x x x x x x x x x x A12 x x x x x x x x x x x x x x x x Size
(2/2)
Sector
128K words (4 Sectors) SA71 to SA74 128K words (4 Sectors) SA75 to SA78 128K words (4 Sectors) SA79 to SA82 128K words (4 Sectors) SA83 to SA86 128K words (4 Sectors) SA87 to SA90 128K words (4 Sectors) SA91 to SA94 128K words (4 Sectors) SA95 to SA98 128K words (4 Sectors) SA99 to SA102 128K words (4 Sectors) SA103 to SA106 128K words (4 Sectors) SA107 to SA110 128K words (4 Sectors) SA111 to SA114 128K words (4 Sectors) SA115 to SA118 128K words (4 Sectors) SA119 to SA122 128K words (4 Sectors) SA123 to SA126 128K words (4 Sectors) SA127 to SA130 96K words (3 Sectors) SA131 to SA133
Remark x : VIH or VIL
12
Data Sheet M16062EJ2V0DS
PD29F064115-X
Product ID Code (Manufacturer Code / Device Code)
Product ID Code Output code I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Manufacturer Code Device code Sector group protection 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 1 HEX 0010H 221CH 0001H Note
Note If 0001H is output, the sector group is protected. If 0000H is output, the sector group is unprotected.
Data Sheet M16062EJ2V0DS
13
PD29F064115-X
Command Sequence
Command sequence Bus 1st bus Cycle Data F0H AAH AAH B0H 30H AAH AAH B0H 30H AAH A0H 80H 80H 90H AAH 2nd bus Cycle Address RA 2AAH 2AAH - - 2AAH 2AAH - - 2AAH PA xxxH SA xxxH 2AAH Data RD 55H 55H - - 55H 55H - - 55H PD 10H 30H 00H
Note11
3rd bus Cycle Address - 555H 555H - - 555H 555H - - 555H - - - - (BA) 555H Data - F0H A0H - - 80H 80H - - 20H - - - - 90H
4th bus Cycle Address - RA PA - - 555H 555H - - - - - - - IA Data - RD PD - - AAH AAH - - - - - - - ID
5th bus Cycle Address - - - - - 2AAH 2AAH - - - - - - - - Data - - - - - 55H 55H - - - - - - - -
6th bus Cycle Address - - - - - 555H SA - - - - - - - - Data - - - - - 10H 30H - - - - - - - -
Cycle Address Read / Reset Read / Reset Program Program Suspend Program Resume Chip Erase Sector Erase Sector Erase Suspend Sector Erase Resume Unlock Bypass Set Unlock Bypass Program
Note 7 Note 7 Note 7 Note 4, 5 Note 4, 6 Note 2 Note 3 Note1 Note1
1 3 4 1 1 6 6 1 1 3 2 2 2 2 3
xxxH 555H 555H BA BA 555H 555H BA BA 555H xxxH xxxH xxxH xxxH 555H
Unlock Bypass Chip Erase
Unlock Bypass Sector Erase Unlock Bypass Reset
Note 7
Product ID / Sector Group Protection Information / Read Mode Register Information Sector Group Protection Sector Group Unprotect
Note 8 Note 9
55H
4 4 3 4
xxxH xxxH 555H 555H
60H 60H AAH AAH
SPA SUA 2AAH 2AAH
60H 60H 55H 55H
SPA SUA 555H 555H
40H 40H 88H 90H
SPA SUA - xxxH
SD SD - 00H
- - - -
- - - -
- - - -
- - - -
Extra One Time Protect Sector Entry Extra One Time Protect Sector Reset
Note 10
Extra One Time Protect Sector Program
Note 10
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
-
-
-
-
Extra One Time Protect Sector Erase
Note 10
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
EOTPSA
30H
Extra One Time Protect Sector Protection
Note 10
4
xxxH
60H
EOTPSA
60H
EOTPSA
40H
EOTPSA
SD
-
-
-
-
Read Mode Register Set
3
555H
AAH
2AAH
55H
REGD
C0H
-
-
-
-
-
-
14
Data Sheet M16062EJ2V0DS
PD29F064115-X
Notes 1. Both these read / reset commands reset the device to the read mode. 2. Programming is suspended if B0H is input to the bank address being programmed to in a program operation. 3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend operation. 4. If automatic erase resume and suspend are repeated at intervals of less than 100 s, since it will become suspend operation, without starting automatic erase, the erase operation may not be correctly completed. 5. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation. 6. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend operation. 7. Valid only in the Unlock Bypass mode. 8. Valid only in /RESET = VID (except in the Extra One Time Protect Sector mode). 9. The command sequence that protects a sector group is excluded. 10. Valid only in the Extra One Time Protect Sector mode. 11. This command can be used even if this data is F0H. Remarks 1. The system should generate the following address pattern: 555H or 2AAH (A10 to A0) 2. RA RD IA : Read address : Read data : Address input as follows
Information Manufacturer code Device code Sector group protection information Read mode register information A21 to A12 Bank address Bank address Sector group address Bank address A11 to A4 Don't care Don't care Don't care Don't care A3 to A0 0000 0001 0010 0100
ID
: Code output. For the manufacture code, device code and sector group protection information, refer to the Product ID code (Manufacture Code / Device Code). For read mode register information, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
PA PD SA BA
: Program address : Program data : Erase sector address. The sector to be erased is selected by the combination of A21 to A12. Refer to the Sector Organization / Sector Address Table. : Bank address. Refer to the Sector Organization / Sector Address Table.
Data Sheet M16062EJ2V0DS
15
PD29F064115-X
SPA
: Sector group address to be protected or protection-verified. Set the sector group address (SGA) and (A6, A3, A2, A1, A0) = (VIL, VIL, VIL, VIH, VIL). Sector group protection can be set for each sector group address. For details, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). Refer to the Sector Group Address Table for the sector group address.
SUA
: Sector group address to be unprotected or unprotection-verified. Set the sector group address (SGA) and (A6, A3, A2, A1, A0) = (VIH, VIL, VIL, VIH, VIL). Sector group unprotect is performed for all sector group using a single command, however, unprotect verification must be performed for each sector group address. For details, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). Refer to the Sector Group Address Table for the sector group address.
EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 000000H to 007FFFH. SD REGD : Data for verifying whether sector groups read from the address specified by SPA, SUA, EOTPSA are protected or unprotected. : Read mode register information. Description for setting, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). 3. The sector group address is don't care except when a program / erase address or read address are selected. 4. For the operation of bus, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). 5. x of address bit indicates VIH or VIL.
BUS OPERATIONS, COMMANDS, HARDWARE SEQUENCE FLAGS, HARDWARE DATA PROTECTION Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
16
Data Sheet M16062EJ2V0DS
PD29F064115-X
Electrical Characteristics
Before turning on power, input GND 0.2 V to the /RESET pin until VCC VCC (MIN.) and keep that state for 200 s. Absolute Maximum Ratings
Parameter Supply voltage Input / Output supply voltage Input voltage VIN with respect except /WP(ACC), /RESET to GND Input /Output voltage Ambient operation temperature Storage temperature Tstg Tbias at bias -65 to +150 -25 to +85 VI/O TA /WP(ACC), /RESET -0.5 -0.5 Note 1 to VCCQ + 0.5 Note 2 -0.5
Note 1 Note 1
Symbol VCC VCCQ
Condition with respect to GND with respect to GND
Rating -0.5 to +2.4 -0.5 to +4.0
Unit V V
V
to +13.0 V
with respect to GND
to VCCQ + 0.5 Note 2
-25 to +85
C C
Notes 1. -2.0 V (MIN.) (pulse width 20 ns) 2. VCCQ + 2.0 V (MAX.) (pulse width 20 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Symbol Test condition -DB80X, -DB85X MIN. Supply voltage Input / Output supply voltage High level input voltage VCC VCCQ VIH VID High voltage is applied (/RESET) Low level input voltage Accelerated programming voltage Ambient operating temperature TA VIL VACC High voltage is applied -25 +85 -25 +85 C -0.5 Note2 8.5 +0.5 9.5 -0.5 Note2 8.5 +0.5 9.5 V V 1.8 2.7 2.4 9.0 MAX. 2.1 3.3 VCCQ+0.3 11.0
Note1
-EB85X, -EB90X MIN. 1.65 2.7 2.4 9.0 MAX. 1.95 3.3 VCCQ+0.3 11.0
Note1
Unit
V V V V
Notes 1.
VCCQ + 0.6 V (MAX.) (pulse width 20 ns)
2. -0.6 V (MIN.) (pulse width 20 ns)
Data Sheet M16062EJ2V0DS
17
PD29F064115-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition -DB80X, -DB85X MIN. High level output voltage VOH1 IOH = -2.0 mA, VCC = VCC (MIN.), VCCQ = VCCQ (MIN.) VOH2 IOH = -100 A, VCC = VCC (MIN.), VCCQ = VCCQ (MIN.) Low level output voltage Input leakage current High voltage is applied I/O leakage current Power supply current Standby ICC3 Read Program, Erase VOL ILI1 ILI2 ILO ICC1 ICC2 IOL = 4.0 mA, VCCQ = VCCQ (MIN.) VIN = GND to VCCQ, VCCQ = VCCQ (MAX.) /RESET = 11.0 V VI/O = GND to VCCQ, VCCQ = VCCQ (MAX.) /CE = VIL, /OE = VIH, Cycle = 5 MHz, IOUT = 0 mA /CE = VIL, /OE = VIH, Automatic programming / erase VCC = VCC(MAX.) , /OE = VIL, /CE = /RESET = /WP(ACC) = VCCQ 0.3 V Standby / Reset Automatic sleep mode Read during programming Read during erasing Programming during suspend Accelerated programming Low VCC lock-out voltage
Note
(1/2)
Unit
TYP.
MAX. V
2.4
VCCQ-0.1
0.45 1.0 35 1.0 10 20 35
V
A
A
mA mA
15
25
A A A
mA
ICC4 ICC5 ICC6
VCC = VCC (MAX.), /RESET = GND 0.2 V VIH = VCCQ 0.2 V, VIL = GND 0.2 V VIH = VCCQ 0.2 V, VIL = GND 0.2 V
15 15
25 25 55
ICC7 ICC8
VIH = VCCQ 0.2 V, VIL = GND 0.2 V /CE = VIL, /OE = VIH, Automatic programming during suspend
55 35
mA mA
IACC
/WP (ACC) pin VCC
5 15 1.0
10 35
mA
VLKO
V
Note When VCC is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). Remark VIN : Input voltage, VI/O : Input / Output voltage
18
Data Sheet M16062EJ2V0DS
PD29F064115-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition -EB85X, -EB90X MIN. High level output voltage VOH1 IOH = -2.0 mA, VCC = VCC (MIN.), VCCQ = VCCQ (MIN.) VOH2 IOH = -100 A, VCC = VCC (MIN.), VCCQ = VCCQ (MIN.) Low level output voltage Input leakage current High voltage is applied I/O leakage current Power supply current Standby ICC3 Read Program, Erase VOL ILI1 ILI2 ILO ICC1 ICC2 IOL = 4.0 mA, VCCQ = VCCQ (MIN.) VIN = GND to VCCQ, VCCQ = VCCQ (MAX.) /RESET = 11.0 V VI/O = GND to VCCQ, VCCQ = VCCQ (MAX.) /CE = VIL, /OE = VIH, Cycle = 5 MHz, IOUT = 0 mA /CE = VIL, /OE = VIH, Automatic programming / erase VCC = VCC(MAX.), /OE = VIL, /CE = /RESET = /WP(ACC) = VCCQ 0.3 V Standby / Reset Automatic sleep mode Read during programming Read during erasing Programming during suspend Accelerated programming Low VCC lock-out voltage
Note
(2/2)
Unit
TYP.
MAX. V
2.4
VCCQ-0.1
0.45 1.0 35 1.0 8 15 25
V
A
A
mA mA
15
25
A A A
mA
ICC4 ICC5 ICC6
VCC = VCC (MAX.), /RESET = GND 0.2 V VIH = VCCQ 0.2 V, VIL = GND 0.2 V VIH = VCCQ 0.2 V, VIL = GND 0.2 V
15 15
25 25 40
ICC7 ICC8
VIH = VCCQ 0.2 V, VIL = GND 0.2 V /CE = VIL, /OE = VIH, Automatic programming during suspend
40 25
mA mA
IACC
/WP (ACC) pin VCC
5 12 1.0
10 25
mA
VLKO
V
Note When VCC is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E). Remark VIN : Input voltage, VI/O : Input / Output voltage
Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. 6.0 8.5 MAX. 7.5 12.0 Unit pF pF
Remarks 1. VIN : Input voltage, VI/O : Input / Output voltage 2. These parameters are not 100% tested.
Data Sheet M16062EJ2V0DS
19
PD29F064115-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 5 ns)
VCCQ VCCQ / 2 0V Test points VCCQ / 2
Output Waveform
VCCQ / 2
Test points
VCCQ / 2
Output Load 1 TTL + 30 pF
20
Data Sheet M16062EJ2V0DS
PD29F064115-X
Read Cycle
Parameter Symbol -DB80X -DB85X -EB85X MIN. Read cycle time Address access time Page read cycle time Page address access time /CE access time /OE access time Output disable time Output hold time /RESET pulse width /RESET hold time before read /RESET low At automatic mode tRC tACC tPRC tPACC tCE tOE tDF tOH tRP tRH tREADY 0 500 50 20 500 tOEH 20 20 30 30 80 25 25 0 500 50 20 500 20 80 80 30 30 85 25 25 0 500 50 20 500 MAX. MIN. 85 85 30 30 90 25 25 MAX. MIN. 90 90 MAX. ns ns ns ns ns ns ns ns ns ns 1 2 1 -EB90X Unit Note
s
ns ns
to read mode Except automatic mode /OE low level time from /WE high level
Notes 1. /CE = /OE = VIL 2. /OE = VIL Remark tDF is the time from inactivation of /CE or /OE to high impedance state output.
Data Sheet M16062EJ2V0DS
21
PD29F064115-X
Write Cycle (Program / Erase)
Parameter Symbol -DB80X -DB85X -EB85X MIN. Write cycle time Address setup time (/WE to address) Address setup time (/CE to address) Address hold time (/WE to address) Address hold time (/CE to address) Input data setup time Input data hold time /OE hold time Read Toggle bit, Data polling Read recovery time before write (/OE to /CE) Read recovery time before write (/OE to /WE) /WE setup time (/CE to /WE) /CE setup time (/WE to /CE) /WE hold time (/CE to /WE) /CE hold time (/WE to /CE) Write pulse width /CE pulse width Write pulse width high /CE pulse width high Word programming operation time Chip programming operation time Sector erase operation time 4K words sector 32K words sector 4K words sector 32K words sector Chip erase operation time tCER tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWPG tCPG tSER tWC tAS tAS tAH tAH tDS tDH tOEH 80 0 0 45 45 45 0 0 10 0 0 0 0 0 0 35 35 30 30 11 47 0.15 0.5 0.5 0.7 65.4 96.2 Accelerated programming time Program / erase cycle VCC setup time RY (/BY) recovery time /RESET pulse width
/RESET high-voltage (VID) hold time from high of RY (/BY) when sector group is temporarily unprotect
(1/2)
-EB90X Unit Note
TYP. MAX. MIN. 85 0 0 45 45 45 0 0 10 0 0 0 0 0 0 35 35 30 30 200 840 1.0 1.5 3.0 5.0 205 678 150
300,000
TYP. MAX. MIN. 90 0 0 45 45 45 0 0 10 0 0 0 0 0 0 35 35 30 30 11 47 0.15 0.5 0.5 0.7 65.4 96.2 7 200 840 1.0 1.5 3.0 5.0 205 678 150
300,000
TYP. MAX. ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns ns ns 11 47 0.15 0.5 0.5 0.7 65.4 96.2 7 200 840 1.0 1.5 3.0 5.0 205 678 150 s 1,2 1,3 1,3
s
s s 1,2
tACCPG
300,000
7
s
cycle
tVCS tRB tRP tRRB
200 0 500 20
200 0 500 20
200 0 500 20
s
ns ns
s
/RESET hold time
tRH
50
50
50
ns
Notes 1. The preprogramming time prior to the erase operation is not included. 2. Program / erase cycle : 100,000 cycles 3. Program / erase cycle : 300,000 cycles
22
Data Sheet M16062EJ2V0DS
PD29F064115-X
Write Cycle (Program / Erase)
Parameter Symbol -DB80X -DB85X -EB85X MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. From completion of automatic program / erase to data output time RY (/BY) delay time from valid program or erase operation Address setup time to /OE low in toggle bit
Address hold time to /CE or /OE high in toggle bit
(2/2)
-EB90X Unit Note
tEOE
80
85
90
ns
tBUSY
80
85
90
ns
tASO tAHT tCEPH tOEPH tVLHT tVIDR tVACCR tTOW tSPD
15 0 20 20 4 500 500 50 20
15 0 20 20 4 500 500 50 20
15 0 20 20 4 500 500 50 20
ns ns ns ns
/CE pulse width high for toggle bit /OE pulse width high for toggle bit Voltage transition time Rise time to VID (/RESET) Rise time to VACC (/WP(ACC)) Erase timeout time Erase suspend transition time
s
ns ns
1
s s
2 2
Notes 1. Sector group protection only. 2. Table only. Write operation (Program / Erase) Performance
Parameter Sector erase time Description The preprogramming time 4K words sector MIN. TYP. 0.15 0.5 0.5 0.7 65.4 96.2 11 47 7 300,000 MAX. 1.0 1.5 3.0 5.0 205 678 200 840 150 s 1 2 2 Unit s Note 1
prior to the erase operation 32K words sector is not included. 4K words sector 32K words sector Chip erase time The preprogramming time prior to the erase operation is not included. Word programming time Chip programming time Accelerated programming time Program / erase cycle Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead
s
s
s
cycle
Notes 1. Program / erase cycle : 100,000 cycles 2. Program / erase cycle : 300,000 cycles
TIMING CHARTS, FLOW CHARTS Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Data Sheet M16062EJ2V0DS
23
PD29F064115-X
Package Drawings
48-PIN PLASTIC TSOP (I) (12x20)
detail of lead end 1 48 F G R
Q 24 25 E P I J A
L S
S K N S
C B D MM
NOTES
1) Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM A B C D E F G I J K L M N P Q R S
MILLIMETERS 12.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 1.00.05 18.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 20.00.2 3+5 -3 0.25 0.600.15 S48GZ-50-MJH-1
24
Data Sheet M16062EJ2V0DS
PD29F064115-X
63-PIN TAPE FBGA (11x8)
E
wSB
ZD
ZE
B
A
8 7 6 5 4 3 2 1 ML K J HGFEDCBA
D
INDEX MARK wSA
ITEM D
MILLIMETERS 8.000.10 11.000.10 0.20 0.970.10 0.270.05 0.70 0.80 0.450.05 0.08 0.10 0.20 1.20 1.10 P63F9-80-CD6
A y1 S A2 S
E w A A1 A2 e b x y y1 ZD ZE
y
S
e
A1
b
x
M
S AB
Data Sheet M16062EJ2V0DS
25
PD29F064115-X
85-PIN TAPE FBGA (11x8)
ZD E wSB ZE B 10 9 8 7 6 5 4 3 2 1 ML K J HGFEDCBA
A
D
INDEX MARK
wSA
A y1 S A2 S
y
S
e
A1
M
b
x
S AB
ITEM D E w e A A1 A2 b x y y1 ZD ZE
MILLIMETERS 8.000.10 11.000.10 0.20 0.80 1.110.10 0.270.05 0.84 0.450.05 0.08 0.10 0.20 0.40 1.10 P85F9-80-CD5
26
Data Sheet M16062EJ2V0DS
PD29F064115-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD29F064115-X. Types of Surface Mount Device
PD29F064115GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) PD29F064115F9-CD6 : 63-pin TAPE FBGA (11 x 8) PD29F064115F9-CD5 : 85-pin TAPE FBGA (11 x 8)
Data Sheet M16062EJ2V0DS
27
PD29F064115-X
Revision History
Edition/ Date This edition 2nd edition/ Sep.2002 Throughout p.16 p.21 Page Previous edition - p.14 p.19 Addition Modification - Command Sequence Read Cycle Preliminary Data Sheet Data Sheet Remark 2 : SPA, SUA tOEH Type of revision Location Description (Previous edition -> This edition)
28
Data Sheet M16062EJ2V0DS
PD29F064115-X
[ MEMO ]
Data Sheet M16062EJ2V0DS
29
PD29F064115-X
[ MEMO ]
30
Data Sheet M16062EJ2V0DS
PD29F064115-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M16062EJ2V0DS
31
PD29F064115-X
Related Document
Document Name PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information Document Number M15451E
* The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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